1. Technical Field
The present invention relates generally to a grooved planar DRAM transfer device, and more particularly pertains to a grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.
In prior art FETs having a grooved trench in the channel, a corner of the groove images charge over a larger area around the semiconductor corner. Thus, a higher gate voltage is needed to image the same density of charge. The effect is like a thicker gate oxide or a lower gate voltage. Sub Vt slope is also degraded because lower coupling to silicon results in less current when the device is on.
2. Prior Art
Grooved planar DRAM transfer devices are described in DRAM Cell WITH GROOVED PLANAR TRANSFER DEVICE, U.S. Ser. No. (docket 10743, BU997-107), the specification of which is expressly incorporated by reference herein, and are promising for very high-density DRAMs (less than 7 square) because of their greatly reduced short channel effects. However, it has been discovered that a gate electric field reduction at the bottom corners of the groove produces electric potential barriers which are deleterious to the electrical characteristics of the device. Furthermore, variations in the geometry of the bottom part of the groove (i.e., variations in the radius of curvature) can cause considerable variations in the electrical performance characteristics of different devices.
Prior art exists which recognizes the degradation in device characteristics due to the bottom corners [IEEE EDL, Vol. 43, No. 8, August 1996, pp. 1251-1255; IEEE TED, Vol. 42, No. 1, January 1995, pp. 94-100; IEEE EDL, Vol. 14, No. 8, August 1993, pp. 396-399]. Moreover, U.S. Pat. No. 5,408,116 seeks to minimize the deleterious effects at the bottom corners by controlling the radius of curvature of the corners to decrease the Vt.
Some prior art describes selectively doping a corner or an edge of a channel to raise Vt of that part of the channel for a DRAM transfer device which is bounded by STI (Shallow Trench Isolation). In that case, the invention seeks to suppress current along an STI bounded edge in a direction which is parallel to the channel. Furthermore, in the prior art the surface of the semiconductor corner which is being doped to raise Vt is convex with respect to the gate conductor. This geometry enhances the gate electric field in the silicon, lowering the Vt and requiring higher doping of the same type as the surrounding semiconductor.
The present invention is distinguished therefrom by the fact that the region being doped extends across the entire width of the channel, so that all current flows through the doped region, and by the fact that the Vt of the region is being lowered. The present invention also distinguishes from the prior art by the fact that N-type doping is provided to lower Vt (in an NMOSFET), and by the fact that the doping cuts across the channel like a crossing walk cuts across a road.
Accordingly, it is a primary object of the present invention to provide an improved grooved planar DRAM transfer device using a buried pocket.
The present invention provides a method for completely eliminating the bottom corner potential barriers and the deleterious influence of the bottom of the groove on the device electrical characteristics, and thereby provides a DRAM transfer MOSFET which is superior to the prior art.
The subject invention provides a pocket at the bottom of the groove with N-type doping, and so does not use the length along the bottom and its corners, just the gain in length along the sidewalls. The doping at the bottom of the groove can be N-type or more lightly doped P-type in an NMOSFET. In a PMOSFET, doping polarities are reversed.
The level of doping modification at the bottom of the grooves depends on the radius of curvature of the bottom corners. Grooves having a small radii of curvature may require complete compensation of the dopant at the bottom of the groove (i.e. P-type dopant in an NMOSFET converted to N-type dopant, an N-type pocket). Where the radius of curvature is large, merely reducing the P-type concentration at the bottom of the groove suffices to lower the threshold voltage to an acceptable level.
The present invention provides a method of eliminating the potential barriers at the bottom corners of the groove, thus resulting in more tightly controlled device characteristics.
The present invention forms a buried N-layer or lightly doped buried P-layer at the bottom of the groove in a grooved NFET device. The buried layer may be formed by an ion implant of an N-type impurity such as phosphorus or arsenic. Implant scattering and subsequent thermal budget result in the spreading of the N-dopant such that the net doping at the bottom corners of the groove becomes N-type. The concept is to lower the Vt at the bottom corners. Depending on radius of curvature of the corners, lightly doped P-type may suffice.
The present invention provides a semiconductor structure having a corner region which is selectively doped to lower the Vt of that region. In greater detail, the semiconductor structure comprises a transistor having a channel, and a groove extending across the channel, and the corner region is a corner of the groove. The transistor comprises a source, a drain, and a channel. The channel has a center region between the source and drain, and selective doping is provided extending across a portion of the center region but not extending to the source and drain.